In order to sophisticate and integrate a control system and an information system in a vehicle, it is important to obtain a higher capacity of a processor for implementing the sophistication and the integration. For example, in order to sophisticate an engine control system playing an important role in development of a vehicle which is safe, comfortable and excellent in fuel economy, an increase in a calculation load, such as a sophistication of a control algorithm or a realization of a new control function is required. In order to solve the above problem, an increase of a processing speed of a processor for realizing a real-time control is indispensable.
However, it is difficult to improve an operating frequency of the processor as in the conventional art because power consumption is increased in proportion to the cube of the frequency. For that reason, multiple processor cores having a low operating frequency are integrated on one chip together, and the processor cores that are reduced in the frequency and the voltage for power consumption reduction are operated in parallel manner, to thereby transit to a multi-core processor that can realize an increase in the processing speed and a reduction in the power consumption at the same time at a rapid pace.
In order that the multi-core processor performs the processing at a higher speed than that of the single-core processor, a process of a sequential program for the single-core processor needs to be divided into sub-processes, and the respective sub-processes need to be assigned to respective processing cores so that a communication among the respective processing cores is minimized. Up to now, the work for parallelizing the sequential program as described above needs to be manually performed. However, such work is very difficult, and requires a long period of time, and suffers from many problems such as an increase in development costs and the reliability of the parallelized program.
JP 2015-001807 A (corresponding to US 2014/0372995 A1) proposes a parallelization compiling method that is capable of creating a parallelized program for a vehicular device built-in system which is high in reliability and can perform high-speed processing while suppressing a development period of time and the development costs.
In the conventional art, when the sequential program prepared for the single-core processor is parallelized once, and thereafter a macro task is added to or deleted from the sequential program, the parallelizing process is performed again. For that reason, a macro task assigned to a first core in a first parallelizing process may be assigned to a second core in a subsequent parallelizing process. That is, the macro task to which no change is carried out compared with a state in which the macro task is included in the first sequential program, that is, the macro task to which no addition or no deletion is carried out may move between the cores. The movement of the macro tasks between or among the cores may cause a substantial change of the overall program and an increase of test man-hours after the parallelization is carried out.